1/6 target data october 2001 STL35NF3LL n-channel 30v - 0.0055 w - 35a powerflat? low gate charge stripfet? mosfet (1)i sd <35a, di/dt<300a/ s, v dd STL35NF3LL 30 v < 0.007 w 35 a symbol parameter value unit v ds drain-source voltage (v gs = 0) 30 v v dgr drain-gate voltage (r gs = 20 k w ) 30 v v gs gate- source voltage 15 v i d (#) drain current (continuos) at t c = 25c drain current (continuos) at t c = 100c 35 22 a a i dm ( l ) drain current (pulsed) 140 a p tot total dissipation at t c = 25c 80 w derating factor 0.64 w/c dv/dt(1) peak diode recovery voltage slope tbd v/ns e as (2) single pulse avalanche energy tbd j t stg storage temperature C55 to 150 c t j max. operating junction temperature powerflat ?(6x5) (chip scale package) internal schematic diagram
STL35NF3LL 2/6 thermal data electrical characteristics (tcase = 25 c unless otherwise specified) off on (1) dynamic rthj-case thermal resistance junction-case max 1.56 c/w rthj-amb thermal resistance junction-ambient max 50 c/w symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 30 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating 1a v ds = max rating, t c = 125 c 10 a i gss gate-body leakage current (v ds = 0) v gs = 15v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs , i d = 250a 1v r ds(on) static drain-source on resistance v gs = 10 v, i d = 17.5 a 0.0055 0.007 w v gs = 4.5 v, i d = 17.5a 0.007 0.010 w symbol parameter test conditions min. typ. max. unit g fs (1) forward transconductance v ds > i d(on) x r ds(on)max, i d = 17.5 a tbd s c iss input capacitance v ds = 25 v, f = 1 mhz, v gs = 0 2650 pf c oss output capacitance 900 pf c rss reverse transfer capacitance 150 pf
3/6 STL35NF3LL electrical characteristics (continued) switching on switching off source drain diode note: 1. pulsed: pulse duration = 300 s, duty cycle 1.5 %. 2. pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time v dd = 15 v, i d = 17.5 a r g = 4.7 w v gs = 4.5v (see test circuit, figure 3) tbd ns t r rise time tbd ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 15 v, i d = 35 a, v gs = 10 v 80 tbd tbd nc nc nc symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off-delay time fall time v dd = 15 v, i d = 17.5 a, r g =4.7 w, v gs = 4.5 v (see test circuit, figure 3) tbd tbd ns ns symbol parameter test conditions min. typ. max. unit i sd source-drain current 35 a i sdm (1) source-drain current (pulsed) 140 a v sd (2) forward on voltage i sd = 35 a, v gs = 0 1.2 v t rr q rr i rrm reverse recovery time reverse recovery chargereverse recovery current i sd = 35 a, di/dt = 100a/s, v dd = 30 v, t j = 150c (see test circuit, figure 5) tbd tbd tbd ns nc a
STL35NF3LL 4/6 fig. 5: test circuit for inductive load switching and diode recovery times fig. 4: gate charge test circuit fig. 2: unclamped inductive waveform fig. 1: unclamped inductive load test circuit fig. 3: switching times test circuit for resistive load
5/6 STL35NF3LL dim. mm. inch min. typ max. min. typ. max. a 0.80 1.00 0.031 0.039 a1 0.08 0.003 b 0.36 0.48 0.014 0.018 d 4.89 0.191 d2 3.95 4.05 0.154 0.158 e 6.00 0.235 e2 2.95 3.05 0.115 0.119 e 1.27 0.049 l 0.65 0.85 0.025 0.033 powerflat ? (6x5) mechanical data
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